This invention relates to a semiconductor memory device.
The semiconductor memory device is indispensably used for a main memory of a computer system. In general, the semiconductor memory device is composed of a plurality of memory cells matrix arrayed on a semiconductor chip, and row and column decoders for decoding row and column address signals. The row decoder is connected to work lines laid in rows of a matrix array of the memory cells. The memory cells arrayed in the same row are selected by the row decoder through an associated one of the word lines. Bit lines are laid in the columns of the matrix array to transfer data to and from the memory cells. The column decoder selects the bit lines according to the column address signal. Data to be written is supplied from the data line to one of the bit lines, and data read out from the cells is transferred from one of the bit lines to the data line.
The dynamic RAMs have predominantly been used recently for high density semiconductor memory devices. The memory cell of the dynamic RAM has a relatively simple structure in that there are essential elements, for example, a capacitor and a transfer gate. The current path of the transfer gate is connected between the capacitor and the bit line. The conduction state of the transfer gate is controlled by the row decoder through the associated word line. The memory cell stores binary data "0" or "1" according to the amount of charge an the capacitor. Charge in the capacitor tends to decrease with time due to leakage current in the semiconductor chip. In the dynamic RAM, therefore, the memory cells must be refreshed to maintain their validity before data in the capacitor becomes too volatile due to the current leak.
To refresh the memory cell when data in that memory cell is read out, the same data rewritten into the same memory cell. Specifically, a bit line is precharged to a predetermined potential, e.g., 5V. Then, the transfer gate is turned on, and the potential of the bit line is varied according to the charge amount of the capacitor. A sense amplifier, for example, senses a potential variation of the bit line to determine the contents of the memory cell. The sense amplifier sets the bit line potential to 0V or 5V according to the sensed data, which either charges or discharges the capacitor. Then, the transfer gate is turned off, so that a predetermined amount of charge is held in the capacitor.
In a large dynamic RAM of, for example 256K bits, each capacitor cannot store much charge, because the capacitors are discretely manufactured and minute. Therefore, it is conventional to refresh all of the memory cells of the dynamic RAM cyclically at periods of 4 ms or less. If the refresh cycle has a period of more than 4 ms, the data in the memory cells may be altered into erroneous data with a great possibility.
Usually, in the dynamic RAMs, the refresh operation and the normal operation (i.e., read/write operation) are assigned to independent time bands, and the memory cells are periodically refreshed. In the refresh mode, all of the bit lines are used for refreshing the memory cells in a specific row. For this reason, these bit lines can not be used for the read/write operation. To avoid an erroneous operation, access to the dynamic RAM is prohibited during the refresh operation. This is one of the major factors which reduces the effective access speed of the dynamic RAM.
In designing the computer system using the dynamic RAM, a designer always allows for the refresh timings of the dynamic RAM. This greatly increases the designer's task.
This problem also affects the layout and the connection of the components. Switching circuits whose conductive states are controlled by the column decoder are provided in the vicinity of the ends of the bit lines. The data line is connected through these switching circuits to the bit lines. This causes each of, the bit lines to have a relatively large stray capacitance. For example, if in a read mode one of the switching circuits is made conductive, the potential on the precharged data line varies with that on the associated bit line. If the stray capacitance is large, a great deal of time is taken for setting up the data line to a predetermined potential. Therefore, use of the bit lines for the next memory access is prohibited until that potential variation terminates. Thus, the time delay by the data line restricts the speed of the dynamic RAM operation.